1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit.
2. Description of the Related Art
A conventional PLL circuit, as shown in FIG. 6, is formed of a phase comparator 101, a charge pump circuit 102, a loop filter 103, a voltage control oscillator (VCO) 104, and a frequency divider 105. In such a PLL circuit constructed as described above, if the output current of the charge pump circuit 102 is denoted as Ip, the constants of the loop filter 103 as R and C, the sensitivity of the voltage control oscillator 104 as Ko, and the frequency-division ratio of the frequency divider 105 as N, the response of the phase of an output signal with respect to a phase change of an input signal is expressed by the following equation. ##EQU1## where .omega..sub.n is the natural angular frequency and .zeta. is the dumping coefficient, each of which is expressed as follows: ##EQU2## A-3db response band is expressed by the following equation. ##EQU3##
That is, in a region where the dumping coefficient .zeta. is large, the response band is proportional to the product of the sensitivity Ko of the voltage control oscillator 104, the output current Ip of the charge pump circuit 102, and the constant R of the loop filter 103, i.e., loop gain.
Meanwhile, in a case in the whole PLL circuit is assembled into one semiconductor integrated circuit, all of the voltage control oscillator 104, resistors within the charge pump circuit 102, and resistors within the loop filter 103 have manufacturing variations controlled by a strong proportional correlation. Therefore, the output current Ip of the charge pump circuit 102 and the constant R of the charge pump circuit 102 tend to be inversely proportional, and their product is not susceptible to manufacturing variations. However, since the response band varies due to manufacturing variations in the sensitivity Ko of the voltage control oscillator 104, it is difficult to precisely control the response band of the PLL circuit.